? semiconductor components industries, llc, 2008 november, 2008 ? rev. 10 1 publication order number: mc100lvel38/d mc100lvel38 3.3v?ecl 2, 4/6 clock generation chip description the mc100lvel38 is a low skew 2, 4/6 clock generation chip designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the device can be driven by either a differential or single-ended input signal. the common enable (en ) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is en abled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are refe renced to the negative edge of the clock input. the phase_out output will go hi gh for one cloc k cycle whenever the 2 and the 4/6 outputs are both trans itioning from a low to a high. this output allows for clock synchronization within the system. upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple lvel38s, the master reset (mr) input must be asserted to ensure synchr onization. for systems which only use one lvel38, the mr pin need not be exercised as the internal divider design ensures synchronization between the 2 and the 4/6 outputs of a single device. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. features ? 50 ps maximum output-to-output skew ? synchronous enable/disable ? master reset for synchronization ? esd protection: >2 kv human body model ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 3.0 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ? 3.0 v to ? 3.8 v ? internal input 75 k pulldown resistors ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity pb = level 1 pb ? free = level 3 for additional information, see application note and8003/d ? flammability rating: ul 94 v ? 0 @ 0.125 in, oxygen index: 28 to 34 ? transistor count = 388 devices ? pb ? free packages are available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 6 of this data sheet. ordering information *for additional marking information, refer to application note and8002/d. marking diagram* a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package so ? 20 wb dw suffix case 751d 20 1 100lvel38 awlyywwg
mc100lvel38 http://onsemi.com 2 clk figure 1. pinout: 20-lead soic (top view) clk mr v cc 17 18 16 15 14 13 12 4 3 5678 9 q0 11 10 q1 q1 q2 q2 q3 q3 v ee en 19 20 2 1 v cc q0 div_sel v bb v cc warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. phase_out phase_out phase out logic clk clk en mr divsel 2 q0 q0 q1 q1 4/6 q2 q2 q3 q3 phase_out phase _out figure 2. logic diagram r r r r v bb table 1. pin description pin function clk, clk ecl diff clock inputs q 0 , q 1; q 0 , q 1 ecl diff 2 outputs q 2 , q 3; q 2 , q 3 ecl diff 4/6 outputs en ecl sync enable input mr ecl master reset input divsel ecl frequency select input phase_out, phase_out ecl phase sync diff. signal output v bb reference voltage output v cc positive supply v ee negative supply table 2. function table clk en mr function z zz x l h x l l h divide hold q 0 ? 3 reset q 0 ? 3 z = low-to-high transition zz = high-to-low transition x = don?t care dvsel q 2 , q 3 outputs l h divide by 4 divide by 6
mc100lvel38 http://onsemi.com 3 clk q ( 2) q ( 4) q ( 6) phase_out ( 4) phase_out ( 6) figure 3. timing diagrams table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc = 0 v ? 8 to 0 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 to 0 ? 6 to 0 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm soic ? 20 soic ? 20 90 60 c/w c/w jc thermal resistance (junction ? to ? case) standard board soic ? 20 30 to 35 c/w t sol wave solder pb pb ? free <2 to 3 sec @ 248 c <2 to 3 sec @ 260 c 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
mc100lvel38 http://onsemi.com 4 table 4. lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 1) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 50 60 50 60 54 65 ma v oh output high voltage (note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage (single ? ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single ? ended) 1490 1825 1490 1825 1490 1825 mv v bb output voltage reference 1.92 2.04 1.92 2.04 1.92 2.04 v v ihcmr input high voltage common mode range (differential) (note 6) 1.65 2.75 1.65 2.75 1.65 2.75 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 resistor to v cc ? 2.0 v. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min and 1.0 v. table 5. lvnecl dc characteristics v cc = 0.0 v; v ee = ? 3.3 v (note 4) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 50 60 50 60 54 65 ma v oh output high voltage (note 5) ? 1085 ? 1005 ? 880 ? 1025 ? 955 ? 880 ? 1025 ? 955 ? 880 mv v ol output low voltage (note 5) ? 1830 ? 1695 ? 1555 ? 1810 ? 1705 ? 1620 ? 1810 ? 1705 ? 1620 mv v ih input high voltage (single ? ended) ? 1165 ? 880 ? 1165 ? 880 ? 1165 ? 880 mv v il input low voltage (single ? ended) ? 1810 ? 1475 ? 1810 ? 1475 ? 1810 ? 1475 mv v bb output voltage reference ? 1.38 ? 1.26 ? 1.38 ? 1.26 ? 1.38 ? 1.26 v v ihcmr input high voltage common mode range (differential) (note 6) ? 1.65 ? 0.55 ? 1.65 ? 0.55 ? 1.65 ? 0.55 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 5. outputs are terminated through a 50 resistor to v cc ? 2.0 v. 6. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min and 1.0 v.
mc100lvel38 http://onsemi.com 5 table 6. ac characteristics v cc = 3.3 v; v ee = 0.0 v or v cc = 0.0 v; v ee = ? 3.3 v (note 7) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max fmax maximum toggle frequency (figure 4) divide by 2 divide by 4, divide by 6 1.0 0.8 1.2 0.82 1.0 0.8 1.2 0.82 1.0 0.8 1.2 0.82 ghz t plh t phl propagation delay to output clk to q (differential) clk to q (single ? ended) clk to phase_out (differential) clk to phase_out (single ? ended) mr to.q 810 710 800 750 510 1010 1010 1000 1050 810 850 750 840 790 540 1050 1050 1040 1090 840 900 800 890 840 570 1100 1100 1090 1140 870 ps t skew within-device skew (note 8) q 0 ? q 3 all 50 75 50 75 50 75 ps part-to-part q 0 ? q 3 (differential) all 200 240 200 240 200 240 t s setup time en to clk divsel to clk 150 150 150 ps t h hold time clk to en clk to div_sel 150 200 150 200 150 200 ps v pp input swing (note 9) clk 250 1000 250 1000 250 1000 mv t rr reset recovery time 100 100 100 ps t pw minimum pulse width clk mr 800 700 800 700 800 700 ps t r , t f output rise/fall times q (20% ? 80%) 280 550 280 550 280 550 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. v ee can vary 0.3 v. 8. skew is measured between outputs under identical transitions. 9. v pp (min) is minimum input swing for which ac parameters are guaranteed. the device will function reliably with differential inputs down to 100 mv. figure 4. fmax: voutpp vs input frequency per div2/4/6
mc100lvel38 http://onsemi.com 6 figure 5. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package package ? MC100LVEL38DW soic ? 20 38 units / rail MC100LVEL38DWg soic ? 20 (pb ? free) 38 units / rail MC100LVEL38DWr2 soic ? 20 1000 / tape & reel MC100LVEL38DWr2g soic ? 20 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc100lvel38 http://onsemi.com 7 package dimensions 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition. so ? 20 wb dw suffix case 751d ? 05 issue g on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hol d scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc100lvel38/d eclinps are registered trademarks of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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